Output power control system

ABSTRACT

An output power control system includes an amplifier configured to supply a first current, a reference source configured to supply a second current which is proportional to and less than the first current, and a feedback converter responsive to the second current to control a gain of the amplifier.

THE FIELD OF THE INVENTION

[0001] The present invention relates to an output power control system,and more particularly, to an output power control system for controllingoutput power from a power amplifier in a radio-frequency transmitter.

BACKGROUND OF THE INVENTION

[0002] Radio-frequency transmitters are used to transmit radio-frequencysignals in a variety of applications. Typically the transmitters aredesigned to meet standards that specify output power levels and outputsignal rise and fall times. In many applications, output power controlcircuits or systems control the output power from power amplifiersemployed in the radio-frequency transmitters. One type of output powercontrol circuit includes a feedback loop that feeds back a portion ofthe output signal to an input of the power amplifier to control theoutput power. One standard that is used is the EIA Interim Standard,IS-19-B, 3.1.3.3, January 1988, USA, for the 800 MHz cellular subscriberunits of the EIA system. For example, this standard specifies that therise and fall times of the transmitted output power signal be less thantwo milliseconds.

[0003] A conventional output power control circuit 10 for controllingthe output power of a power amplifier 12 is illustrated in FIG. 1.Output power control circuit 10 is a voltage-controlled output powercontrol circuit which couples a percentage of the transmitted outputpower signal through a detector diode circuit. Power amplifier 12 has avoltage supply connection at 18 and a ground connection at 20. Poweramplifier 12 transmits an input signal received at an input 14 andprovides an output signal at an output 22. The output signal at output22 is routed through a coupler 24 to provide an output signal at 26. Aportion of the output power sent through coupler 24 is routed to aninput 28 of a signal detector 30. Signal detector 30 responds to thepeak level of the output signal at 26. Signal detector 30 includes adetecting diode and produces a detection signal at 34. A comparator 32compares a reference voltage at 36 with the detection signal at 34.Comparator 32 provides an automatic power control voltage (Vapc) to aninput 16 of power amplifier 12 to bring the detection signal at 34 inconformity with the reference voltage at 36.

[0004] One disadvantage of the conventional output power controlapproach employed by output power control circuit 10 are losses whichreduce available output power and system efficiency. The couplerstypically available for radio-frequency amplification systems are large,expensive, and have poor directivity characteristics. The poordirectivity of the couplers results in poor output power accuracy,especially when the radio-frequency load impedance varies. Since thepeak current loads of the power amplifiers are not monitored with thisapproach, the currents can be driven well above nominal levels undercertain operating conditions, thereby further reducing systemefficiency. For battery applications such as for mobile telephones, theresult is a reduction in available talk time.

[0005] Another conventional approach used to control the output power ofa power amplifier 42 is illustrated in FIG. 2. FIG. 2 illustrates aconventional current-controlled output power control circuit 40 whichuses a sense resistor 54 in series with the voltage supply connection at56 to develop a voltage proportional to the power amplifier 42 current.Power amplifier 42 has an input signal at 44 and an output signal at 52.Power amplifier 42 has a voltage supply connection at 48 which iscoupled to one end of a sense resistor 54, and has a ground connectionat 50. Sense resistor 54 is coupled at the other end to the voltagesupply at 56. Capacitor 57 is coupled across sense resistor 54 betweenthe voltage supply at 56 and the connection at 48 of power amplifier 42to shunt instantaneous currents around sense resistor 54 so that senseresistor 54 conducts an average current.

[0006] The approach illustrated in FIG. 2 uses a feedback loop toconvert a current through sense resistor 54 to a power control voltageat 46. A comparator 58 provides a voltage at 50 which corresponds to thecurrent through sense resistor 54. Comparator 62 compares the voltage at50 to a reference voltage at 64 and provides an automatic power controlvoltage (Vapc) at 46 to control the gain of power amplifier 42.

[0007] One disadvantage of this second approach are losses which reduceavailable output power and system efficiency. The sense resistors can beexpensive and can be physically large. The sense resistors can alsocause significant voltage drops which reduce the output poweravailability and efficiency of the power amplifier. This approach alsohas the disadvantage of having the total power amplifier current beingfed back within the control loop. This can result in a loss of powercontrol accuracy because the total current does not necessarily vary indirect proportion to the output power.

[0008] In view of the above, there is a need for an improved outputpower control system such as employed for controlling output power froma power amplifier in a radio-frequency transmitter.

SUMMARY OF THE INVENTION

[0009] One aspect of present invention provides an output power controlsystem which includes an amplifier configured to supply a first current,a reference source configured to supply a second current which isproportional to and less than the first current, and a feedbackconverter responsive to the second current to control a gain of theamplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 illustrates a conventional voltage-controlled output powercontrol circuit.

[0011]FIG. 2 illustrates a conventional current-controlled output powercontrol circuit.

[0012]FIG. 3 is a diagram illustrating one exemplary embodiment of anoutput power control circuit according to the present invention.

[0013]FIG. 4 is a diagram illustrating one exemplary embodiment of apower amplifier.

[0014]FIG. 5A is a diagram illustrating the output signal power versustime for an exemplary embodiment of an output power control circuit.

[0015]FIG. 5B is a diagram illustrating an output current I₁ and areference current I₂ versus time for an exemplary embodiment of anoutput power control circuit.

[0016]FIG. 5C is a diagram illustrating a power control voltage versustime for an exemplary embodiment of an output power control circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificembodiments in which the invention may be practiced. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

[0018]FIG. 3 is a diagram illustrating one exemplary embodiment of anoutput power control circuit or system 40 according to the presentinvention for controlling the output power of a power amplifier 72. Inthe illustrated embodiment, power amplifier 72 has a transmission inputsignal at 74 and an output signal at 82. In one embodiment, thetransmission input signal at 74 and the output signal at 82 areradio-frequency signals and power amplifier 72 is a radio-frequencyamplifier. In the exemplary embodiment, power amplifier 72 is coupled toground at 83.

[0019] Power amplifier 72 includes two connections to a voltage supply(Vsupply) provided at a node 80. The voltage supply at node 80 iscoupled to power amplifier 72 via a line 81 which conducts a firstcurrent or output current (I₁) to an output stage 94 (shown in FIG. 4)of power amplifier 72. A feedback resistor 84 is coupled between thevoltage supply at node 80 and a line 78, which is coupled to a secondvoltage supply connection of power amplifier 72. Capacitor 85 is coupledacross feedback resistor 84 between the voltage supply at node 80 andline 78 to shunt instantaneous currents around feedback resistor 84 sothat feedback resistor 84 conducts an average current. Feedback resistor84 conducts the average current which is a second current or referencecurrent (I₂) to a reference current source 96 (shown in FIG. 4) withinpower amplifier 72. In the exemplary embodiment, the reference currentI₂ is proportional to and less than the output current I₁.

[0020] In the exemplary embodiment, a current-to-voltage converterfeedback loop generally indicated at 68 controls the gain of poweramplifier 72. In the exemplary embodiment, the current-to-voltageconverter feedback loop 68 converts the reference current I₂ into apower control voltage to control the gain of power amplifier 72. In theexemplary embodiment, a feedback resistor 84, a first comparator 86, anda second comparator 90 together comprise a negative feedback loop.Feedback resistor 84 conducts the reference current I₂ which creates avoltage drop across resistor 84. First comparator 86 has a positiveinput coupled to node 80 and a negative input coupled to 78 acrossfeedback resistor 84. First comparator 86 compares the supply voltage atnode 80 to the voltage drop across resistor 84 and provides a differencebetween the compared voltages as a voltage on a line 88. Secondcomparator 90 has a negative input coupled to the voltage on line 88 andhas a positive input coupled to a reference voltage (Vref) at 92. Secondcomparator 90 compares the reference voltage Vref at 92 to the voltageon line 88 and provides a difference between the compared voltages as anautomatic power control voltage (Vapc) at 76, which is provided to aninput of power amplifier 72 to control the output power of poweramplifier 72.

[0021] In the exemplary embodiment, the current-to-voltage converterfeedback loop 68 controls the gain of power amplifier 72 so that theoutput signal at 82 conforms with reference voltage Vref at 92. When thereference voltage Vref is increased or decreased, the reference currentI₂, which corresponds to output current I₁ and the power output level,follows the increased or decreased reference voltage Vref.

[0022] In the exemplary embodiment, the reference current I₂ isproportional to and less than the output current I₁. In variousembodiments, the reference current I₂ is smaller than the output currentI₁, which allows a small and economical feedback resistor 84 to beemployed in current-to-voltage converter feedback loop 68. As a result,the small and economical feedback resistor 84 can be implemented with alarger variety of resistor types, which provides greater flexibility inselecting a resistor implementation and in the optimization of loop gainparameters. In various embodiments, reference current I₂ closely tracksoutput power variations at output signal 82 thus providing betterproportional tracking accuracy.

[0023]FIG. 4 is a diagram illustrating one exemplary embodiment of poweramplifier 72. Power amplifier 72 includes an amplifier or output stage94, a reference current source 96, and an input stage 98. In theexemplary embodiment, input stage 98 has a first input coupled to thepower control voltage Vapc at 76 and a second input coupled to thetransmission input signal at 74. In one embodiment, the power controlvoltage Vapc at 76 controls to one or more gates of field effecttransistors (FETs) employed within input stage 98. The amplificationgain is varied by varying the gate voltages so that a predeterminedoutput signal is generated which corresponds to the power controlvoltage Vapc at 76.

[0024] In the exemplary embodiment, input stage 98 has an output 108which is coupled to a gate 106 of a reference transistor 104 inreference current source 96, and a gate 102 of an output transistor 100in output stage 94. Reference current source 96 conducts referencecurrent I₂ via line 78 to ground 83. Output stage 94 conducts outputcurrent I₁ via line 80 to ground 83. Output transistor 100 includes adrain which provides the output signal at 82. In one embodiment,reference transistor 104 and output transistors 100 are complementarymetal-oxide semiconductor (CMOS) transistors. In one embodiment,reference transistor 104 and output transistor 100 are enhancement-modepseudomorphic high-electron mobility (E-pHEMT) transistors. In oneembodiment, reference transistor 104 and output transistor 100 aresilicon bipolar transistors. In one embodiment, reference transistor 104and output transistor 100 are heterojunction bipolar transistors.

[0025] In the exemplary embodiment, reference transistor 104 isproportionally sized to be smaller than output transistor 100 in orderto conduct a smaller current. The ratio of the width-to-length (referredto hereinafter as “W/L”) of a gate of a semiconductor device, such as aCMOS transistor, determines the transistor size and the maximum currentwhich can be conducted by the transistor. Typically the length L of thegate is a fixed value corresponding to a minimum feature size of thesemiconductor fabrication process used to fabricate the transistors.Consequently, the transistor sizes are typically varied by varying thegate width W of the transistor. Two given transistors having twodifferent gate W/L ratios and which are fabricated in close proximity ona given wafer will have comparative current ratios which track withminimal variance from wafer to wafer within a given lot of wafers beingfabricated. In one embodiment, reference transistor 104 and outputtransistor 100 are silicon bipolar transistors and the maximum currentconducted by the transistors is controlled by varying the transistoremitter widths. In one embodiment, reference transistor 104 and outputtransistor 100 are heterojunction bipolar transistors and the maximumcurrent conducted by the transistors is controlled by varying thetransistor emitter widths.

[0026] In the illustrated embodiment, output transistor 100 has a widthαW and reference transistor 104 has a width W. The factor α is aconstant which is used to specify the current ratio of the referencecurrent I₂ to the output current I₁. In various embodiments, thereference current I₂ is smaller than the output current I₁ to minimizelosses to the circuit and to reduce power loss caused by feedbackresistor 84. Since the gate 106 of reference transistor 104 is coupledto the gate 102 of output transistor 100, the reference current I₂ has avalue which is substantially equal to 1/α times the output current I₁.In the exemplary embodiment, the gate length L is substantially the samefor both reference transistor 104 and output transistor 100. In otherembodiments, the gate length L of reference transistor 104 is not thesame as the gate length L of output transistor 100.

[0027] The gate W/L ratios of reference transistor 104 and outputtransistor 100 can be any suitable value. In one example embodiment, theW/L ratio of output transistor 100 is a relatively large value which isgreater than 5000 because output transistor 100 drives the output signalat 82. In this example embodiment, the W/L ratio of reference transistor104 and output transistor 100 is less than 5000. In one embodiment, thevalue of α is 10 such that the W/L ratio of reference transistor 104 is{fraction (1/10)}th of the W/L ratio of output transistor 100 and thereference current I₂ is substantially equal to {fraction (1/10)} timesthe output current I₁. In one embodiment, the value of α is 100 suchthat the W/L ratio of reference transistor 104 is {fraction (1/100)}thof the W/L ratio of output transistor 100 and the reference current I₂is substantially equal to {fraction (1/100)} times the output currentI₁.

[0028]FIG. 5A is a diagram illustrating the output signal power versustime for an exemplary embodiment of output power control circuit 40.FIG. 5B is a diagram illustrating the output current I₁ and thereference current I₂ versus time for an exemplary embodiment of theoutput power control circuit 40. FIG. 5C is a diagram illustrating theautomatic power control voltage Vapc versus time for an exemplaryembodiment of the output power control circuit.

[0029] In the exemplary embodiment, from time T₀ to time T₁, poweramplifier 72 is not activated and is not transmitting the output signalat 82; reference transistor 104 and output transistor 100 are turnedoff; the reference current I₂ and the output current I₁ illustrated inFIG. 5B are zero; the output signal power illustrated in FIG. 5A iszero; and the automatic power control voltage Vapc illustrated in FIG.5C is zero.

[0030] In the exemplary embodiment, at time T₁, a transmission inputsignal at 74 is received by power amplifier 72. The transmission inputsignal at 74 is amplified with a gain by power amplifier 72, and thetransmitted power at output signal 82 begins to rise between time T₁ andtime T₂. In the exemplary embodiment, from T₁ to T₂, output transistor100 is beginning to conduct the output current I₁ and the value of theoutput current I₁ begins to rise. Since the gate 106 of referencetransistor 104 is coupled to the gate 102 of output transistor 100, thereference current I₂ begins to rise as well. In the exemplaryembodiment, the magnitude of the reference current I₂ is less than themagnitude of the output current I₁. FIG. 5B illustrates the outputcurrent I₁ with a dashed line and two values of reference current I₂ forα=10 and α=100 with solid lines. The current axis is shown as broken tosimplify the illustration of the invention, because the referencecurrent I₂ is much smaller than the output current I₁ in the exemplaryembodiment. In the exemplary embodiment, from T₁ to T₂, the value ofreference current I₂ for α=10 and α=100 is substantially equal to avalue of {fraction (1/10)}th and {fraction (1/100)}th, respectively, ofthe output current I₁.

[0031] In the exemplary embodiment, the power control voltage Vapcillustrated in FIG. 5C is the output of the negative feedback loop whichincludes feedback resistor 84, first comparator 86, and secondcomparator 90. In the exemplary embodiment, since the delay of thenegative feedback loop is negligible, the power control voltage Vapcrises in substantially direct proportion to the reference current I₂ tothereby minimize the rise time of the output signal power in FIG. 5A. Asa result, the output signal power level at 82 of power amplifier 72quickly follows the change in the automatic power control voltage Vapcuntil the time T₂, at which the output signal power level at 82corresponds to the automatic power control voltage Vapc at 76. In theexemplary embodiment, the automatic power control voltage Vapc at 76 iscontrolled by the reference voltage Vref at 92 such that the outputsignal power level at 82 also corresponds to the reference voltage Vrefat 92.

[0032] In the exemplary embodiment, at T₂, a desired output signal powerlevel at 82 has been reached and the power control voltage Vapc at 76illustrated in FIG. 5C reaches a steady state. The output current I₁ andthe reference current 12 illustrated in FIG. 5B also reach a steadystate. Since the output current I₁ is at a steady state value, theoutput signal illustrated in FIG. 5A is at a steady state value.

[0033] Although specific embodiments have been illustrated and describedherein for purposes of description of the preferred embodiment, it willbe appreciated by those of ordinary skill in the art that a wide varietyof alternate and/or equivalent implementations calculated to achieve thesame purposes may be substituted for the specific embodiments shown anddescribed without departing from the scope of the present invention.Those with skill in the chemical, mechanical, electromechanical,electrical, and computer arts will readily appreciate that the presentinvention may be implemented in a very wide variety of embodiments. Thisapplication is intended to cover any adaptations or variations of thepreferred embodiments discussed herein. Therefore, it is manifestlyintended that this invention be limited only by the claims and theequivalents thereof.

What is claimed is:
 1. An output power control system, comprising: an amplifier configured to supply a first current; a reference source configured to supply a second current which is proportional to and less than the first current; and a feedback converter responsive to the second current to control a gain of the amplifier.
 2. The output power control system of claim 1, wherein the feedback converter comprises: a current-to-voltage converter for converting the second current into a power control voltage.
 3. The output power control system of claim 2, wherein the current-to-voltage converter comprises: a resistor coupled to a supply voltage to conduct the second current; a first comparator configured to compare the supply voltage to a voltage drop across the resistor and to output a difference between as an output voltage; and a second comparator configured to compare the output voltage to a reference voltage and to output a difference between as the power control voltage.
 4. The output power control system of claim 1, wherein the second current is substantially equal to 1/α times the first current, wherein α is a constant which is greater than one.
 5. The output power control system of claim 4, wherein the amplifier includes: a first transistor having a width αW which conducts the first current.
 6. The output power control system of claim 5, wherein the reference source comprises: a second transistor having a width W which is coupled to the resistor to conduct the second current, wherein a gate of the second transistor is coupled to a gate of the first transistor so that the second current is substantially equal to 1/α times the first current.
 7. The output power control system of claim 6, wherein α is equal to or greater than
 10. 8. The output power control system of claim 6, wherein the first and second transistors are complementary metal-oxide semiconductor transistors.
 9. The output power control system of claim 6, wherein the first and second transistors are enhancement-mode pseudomorphic high-electron mobility transistors.
 10. The output power control system of claim 2, wherein the amplifier further includes: an input stage configured to apply the power control voltage to control the gain.
 11. The output power control system of claim 1, wherein the amplifier is a radio-frequency amplifier.
 12. An output power control system, comprising: an amplifier configured to amplify an input signal with a gain corresponding to a power control voltage to produce an output signal; a mirror reference current source configured to supply a first current and a second current, wherein the second current is proportional to and less than the first current; and a negative feedback converter configured to convert the second current into the power control voltage to control the gain.
 13. The output power control system of claim 12, wherein the negative feedback converter comprises: a resistor coupled to a supply voltage to conduct the second current; a first comparator configured to compare the supply voltage to a voltage drop across the resistor and to output a difference between as an output voltage; and a second comparator configured to compare the output voltage to a reference voltage and to output a difference between as the power control voltage.
 14. The output power control system of claim 13, wherein the mirror reference current source comprises: a first transistor having a width αW to conduct the first current; and a second transistor having a width W which is coupled to the resistor to conduct the second current, wherein a gate of the first transistor is coupled to a gate of the second transistor so that the second current is substantially equal to 1/α times the first current.
 15. The output power control system of claim 14, wherein α is equal to or greater than
 10. 16. The output power control system of claim 14, wherein the first and second transistors are complementary metal-oxide semiconductor transistors.
 17. The output power control system of claim 14, wherein the first and second transistors are enhancement-mode pseudomorphic high-electron mobility transistors.
 18. The output power control system of claim 14, wherein the first and second transistors are silicon bipolar transistors.
 19. The output power control system of claim 14, wherein the first and second transistors are heterojunction bipolar transistors.
 20. A current mirror power control circuit, comprising: a radio-frequency power amplifier having a power control voltage input, wherein the radio-frequency power amplifier amplifies a radio-frequency input signal with a gain corresponding to the power control voltage; a reference transistor having a width W which conducts a reference current; an output transistor having a width αW which conducts an output current which is greater than the reference current, wherein the reference current is proportional to the output current, and wherein the output transistor is configured to provide a radio-frequency output signal; and a negative feedback circuit configured to convert the reference current into the power control voltage.
 21. The current mirror power control circuit of claim 20, wherein the negative feedback converter comprises: a resistor coupled to a supply voltage to conduct the reference current; a first comparison circuit configured to compare the supply voltage to a voltage drop across the resistor and to output a difference between as an output voltage; and a second comparison circuit configured to compare the output voltage to a reference voltage and to output a difference between as the power control voltage.
 22. The current mirror power control circuit of claim 20, wherein α is equal to or greater than
 10. 23. The current mirror power control circuit of claim 20, wherein the reference and output transistors are complementary metal-oxide semiconductor transistors.
 24. The current mirror power control circuit of claim 20, wherein the reference and output transistors are enhancement-mode pseudomorphic high-electron mobility transistors.
 25. A radio-frequency power amplifier, comprising: an input stage configured to control transmission of a radio frequency input signal with a gain corresponding to a power control voltage signal; an output stage configured to provide an output current and a radio-frequency output signal; a reference stage configured to provide a reference current which is proportional to and less than the output current; and a current-to-voltage feedback converter configured to convert the reference current into the power control voltage signal.
 26. The radio-frequency power amplifier of claim 25, wherein the current-to-voltage feedback converter comprises: a resistor coupled to a supply voltage to conduct the reference current; a first comparator configured to compare the supply voltage to a voltage drop across the resistor and to output a difference between as an output voltage; and a second comparator configured to compare the output voltage to a reference voltage and to output a difference between as the power control voltage signal.
 27. The radio-frequency power amplifier of claim 26, wherein the output stage includes: an output transistor having a width αW which conducts the output current.
 28. The radio-frequency power amplifier of claim 27, wherein the reference stage includes: a reference transistor having a width W which is coupled to the resistor to conduct the reference current, wherein a gate of the reference transistor is coupled to a gate of the output transistor so that the reference current is substantially equal to 1/α times the output current.
 29. The radio-frequency power amplifier of claim 28, wherein α is equal to or greater than
 10. 30. The radio-frequency power amplifier of claim 28, wherein the reference and output transistors are complementary metal-oxide semiconductor transistors.
 31. The radio-frequency power amplifier of claim 28, wherein the reference and output transistors are enhancement-mode pseudomorphic high-electron mobility transistors.
 32. The radio-frequency power amplifier of claim 28, wherein the reference and output transistors are silicon bipolar transistors.
 33. The radio-frequency power amplifier of claim 28, wherein the reference and output transistors are heterojunction bipolar transistors.
 34. An output power control system, comprising: an amplifier configured to control a first current; reference means to supply a second current which is proportional to and less than the first current; and feedback means responsive to the second current to control a gain of the amplifier.
 35. The output power control system of claim 34, wherein the feedback means comprises: a current-to-voltage converter for converting the second current into a power control voltage.
 36. The output power control system of claim 35, wherein the feedback means further comprises: a resistor coupled to a supply voltage to conduct the second current; a first comparator configured to compare the supply voltage to a voltage drop across the resistor and to output a difference between as an output voltage; and a second comparator configured to compare the output voltage to a reference voltage and to output a difference between as the power control voltage.
 37. The output power control system of claim 36, wherein the amplifier includes: a first transistor having a width αW which conducts the first current.
 38. The output power control system of claim 33, wherein the reference means comprises: a second transistor having a width W which is coupled to the resistor to conduct the second current, wherein a gate of the second transistor is coupled to a gate of the first transistor so that the second current is substantially equal to 1/α times the first current.
 39. The output power control system of claim 38, wherein α is equal to or greater than
 10. 40. A method of controlling the output power of an amplifier, the method comprising: providing an output current; providing a reference current which is proportional to and less than the output current; and converting the reference current into a power control voltage to control a gain of the amplifier.
 41. The method of claim 40, wherein the converting of the reference current into the power control voltage comprises: comparing the supply voltage to a voltage drop across a resistor and providing a difference between as an output voltage; and comparing the output voltage to a reference voltage and providing a difference between as the power control voltage.
 42. The method of claim 41, wherein the providing of the output current comprises: providing an output transistor having a width αW; and conducting the output current through the output transistor.
 43. The method of claim 42, wherein the providing of the reference current comprises: providing a reference transistor having a width W; coupling a gate of the reference transistor to a gate of the output transistor; and conducting the reference current through the reference transistor wherein the reference current is substantially equal to 1/α times the output current. 